1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that can be preferably applied to a NAND flash memory and a method of reading data from a nonvolatile semiconductor memory device, and more particularly relates to a technique of reducing read disturbance at the time data reading.
2. Description of Related Art
A NAND flash memory is constituted by NAND strings in which a plurality of memory cells each having a floating gate are connected in series and a select transistor is connected to each end. The number of memory cells arranged in the NAND string has been increasing with increase of the capacity of NAND flash memories. At present, 32 cells are mostly arranged in a NAND string for a flash memory having a capacity over 1 megabyte, which is used as a recording medium for storing images taken by a digital camera. In the future, when the memory capacity of NAND flash memories is further increased, it is believed that NAND flash memories having 64 cells arranged in a string will become dominant.
However, conventional NAND flash memories have a problem that an influence of read disturbance increases as the number of cells in a string increases. As described in US 2003-137873-A, read disturbance is caused by an electric field stress exerted on a memory cell connected to an unselected word line because a relatively high voltage is applied to the unselected word line in a selected block (a selected segment) so that the memory cell connected to the unselected word line is turned into a light programming operation state at the time of reading.
FIG. 35 shown a circuit configuration of NAND strings used in a NAND flash memory. As shown in FIG. 35, the NAND string includes a plurality of memory cells M0, M1, connected in series each having a floating gate and select transistors SGD and SGS respectively connected to both ends. The drain of the select transistor SGD is connected to a bit line BL, and the source of the select transistor SGS is connected to a common source line ARVSS.
In each of the NAND strings, gates of the memory cells M0, M1, . . . arranged in a horizontal direction are commonly connected to word lines WL0, WL1, . . . , respectively. The gate of the select transistor SGD is connected to a selected signal line SELD. The gate of the select transistor SGS is connected to a selected signal line SELS.
FIG. 36 is a graph representing a distribution of threshold values of memory cells in conventional NAND strings. As shown in FIG. 36, the threshold values of the memory cells M0, M1, . . . are distributed around 0 volt (V) in a case of data “1” and around 3.5 V in a case of data “0”. Therefore, for example, when a voltage of 6 V is applied to the gates of the memory cells M0, M1, . . . , all the memory cells M0, M1, . . . , are switched on. Meanwhile, for example, when a voltage of 2.5 V is applied to the gates of the memory cells M0, M1, . . . , the memory cells M0, M1, . . . are switched off if the memory cells are programmed and switched on if the memory cells are not programmed.
Therefore, at the time of reading, the voltage of 6 V is applied to gates of unselected memory cells among the memory cells M0, M1, . . . to switch on the unselected memory cells. The voltage of 2.5 V is applied to selected memory cells among the memory cells M0, M1, . . . . In addition, the voltage of 6 V is applied to the gates of the select transistors SGD and SGS to switch on the select transistors SGD and SGS. When a selected memory cell represents data “1”, the selected memory cell is switched on, and when the selected memory cell represents data “0”, the selected memory cell is switched off, so that it is possible to read the data based on whether a current flows through the selected memory cell.
FIG. 37 is a waveform diagram showing voltages of word lines in a conventional NAND flash memory. In the example shown in FIG. 37, a voltage of an unselected word line is set to 6 V and that of a selected word line is set to 2.5 V.
As shown in FIG. 37, first, when the word line WL0 is selected, a selected word line voltage of 2.5 V is applied to the word line WL0 in pulses, and an unselected word line voltage of 6 V is applied to the other word lines WL1, WL2, . . . , WL31 in pulses. Subsequently, when the word line WL1 is selected, the selected word line voltage of 2.5 V is applied to the word line WL1 in pulses, and the unselected word line voltage of 6 V is applied to the other word lines WL0, WL2, . . . , WL31 in pulses. The selected word line voltage of 2.5 V is sequentially applied to the word line WL2, WL3, . . . in pulses, and the unselected word line voltage of 6 V is applied to the other word lines in pulses.
As shown in FIG. 38, the word lines WL0, WL1, . . . and the bit lines BL1, BL2, . . . are wired in a lattice pattern in a memory cell array constituted by NAND strings. A pulse of 0 V, 6 V, 0 V are applied to portions of the word lines WL0, WL1, . . . , when the word lines are not selected. On the other hand, a pulse of 0 V, 2.5 V, 0 V is applied to the word line WL when it is selected. This means that a pulsed stress is applied to the memory cell as shown in FIG. 39B.
As shown in FIG. 39A, a pulsed stress is applied to a memory cell array with a high program voltage of 15 to 20 V when programming the memory cell array. Therefore, as shown in FIG. 39B, an application of the pulse of 0 V, 6 V, 0 V to the portions of the word lines WL0, WL1, . . . when they are not selected at the time of reading can be considered to be equivalent to writing based on a weak-pulsed programming voltage. Even with such a weak programming voltage, the memory cell may be programmed if the number of pulses is further increased. This is the major cause for the read disturbance.
When the number of memory cells in the NAND string is 32, a total of 32 pulses are applied to one memory cell, including a single pulse of 2.5 V when it is selected and 31 pulses of 6 V when it is not selected. If the number of memory cells of the NAND string is increased to 64 or more, the number of pulses applied to word lines at the time of the reading is further increased, so that it is considered that the influence of the read disturbance is increased.
As described above, in conventional NAND flash memories, the voltage of 6 V is applied to the unselected word lines in pulses and the voltage of 2.5 V is applied to the selected word line in pulses at the time of the reading. Conventional NAND flash memories including NAND strings having this configuration has a problem that the influence of the read disturbance increases as the number of strings increases.
In addition, as described above, when the unselected word line voltage is set to 6 V and the selected word line voltage is set to 2.5 V, a high voltage equal to or higher than a power source voltage Vcc needs to be prepared at the time of reading in order to use the unselected word line voltage of 6 V. When the power source voltage Vcc to be supplied as a power source for the memory is 3 V, a power source circuit is required to use the unselected word line voltage of 6 V, which generates a high voltage equal to or higher than 6V from the power source voltage of 3 V. Assuming that this kind of power source circuit is built with a charge pump circuit, the number of stages of charge pump or booster increases, which will cause a longer operation time with a larger power consumption.